Retrograde well structure for a CMOS imager

ABSTRACT

A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

FIELD OF THE INVENTION

[0001] The present invention relates generally to improved semiconductorimaging devices and in particular to a silicon imaging device that canbe fabricated using a standard CMOS process.

BACKGROUND OF THE INVENTION

[0002] There are a number of different types of semiconductor-basedimagers, including charge coupled devices (CCDs), photodiode arrays,charge injection devices and hybrid focal plane arrays. CCD technologyis often employed for image acquisition and enjoys a number ofadvantages which makes it the incumbent technology, particularly forsmall size imaging applications. CCDs are capable of large formats withsmall pixel size and they employ low noise charge domain processingtechniques.

[0003] However, CCD imagers also suffer from a number of disadvantages.For example, they are susceptible to radiation damage, they exhibitdestructive read-out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there have been some attempts to integrate on-chipsignal processing with CCD arrays, these attempts have not been entirelysuccessful. CCDs also must transfer an image by line charge transfersfrom pixel to pixel, requiring that the entire array be read out into amemory before individual pixels or groups of pixels can be accessed andprocessed. This takes time. CCDs may also suffer from incomplete chargetransfer from pixel to pixel which results in image smear.

[0004] Because of the inherent limitations in CCD technology, there isan interest in CMOS imagers for possible use as low cost imagingdevices. A fully compatible CMOS sensor technology enabling a higherlevel of integration of an image array with associated processingcircuits would be beneficial to many digital applications such as, forexample, in cameras, scanners, machine vision systems, vehiclenavigation systems, video telephones, computer input devices,surveillance systems, auto focus systems, star trackers, motiondetection systems, image stabilization systems and data compressionsystems for high-definition television.

[0005] The advantages of CMOS imagers over CCD imagers are that CMOSimagers have a low voltage operation and low power consumption; CMOSimagers are compatible with integrated on-chip electronics (controllogic and timing, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD because standard CMOS processing techniques can beused. Additionally, low power consumption is achieved for CMOS imagersbecause only one row of pixels at a time needs to be active during thereadout and there is no charge transfer (and associated switching) frompixel to pixel during image acquisition. On-chip integration ofelectronics is particularly advantageous because of the potential toperform many signal conditioning functions in the digital domain (versusanalog signal processing) as well as to achieve a reduction in systemsize and cost.

[0006] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate,photoconductor or a photodiode overlying a substrate for accumulatingphoto-generated charge in the underlying portion of the substrate. Areadout circuit is connected to each pixel cell and includes at least anoutput field effect transistor formed in the substrate and a chargetransfer section formed on the substrate adjacent the photogate,photoconductor or photodiode having a sensing node, typically a floatingdiffusion node, connected to the gate of an output transistor. Theimager may include at least one electronic device such as a transistorfor transferring charge from the underlying portion of the substrate tothe floating diffusion node and one device, also typically a transistor,for resetting the node to a predetermined charge level prior to chargetransference.

[0007] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate. For photodiodes, image lag can beeliminated by completely depleting the photodiode upon readout.

[0008] CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12), pp. 2046-2050 (1996); Mendis et al., “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453(1994), as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

[0009] To provide context for the invention, an exemplary CMOS imagingcircuit is described below with reference to FIG. 1. The circuitdescribed below, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

[0010] Reference is now made to FIG. 1 which shows a simplified circuitfor a pixel of an exemplary CMOS imager using a photogate and having apixel photodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

[0011] The photodetector circuit 14 is shown in part as across-sectional view of a semiconductor substrate 16 typically a p-typesilicon, having a surface well of p-type material 20. An optional layer18 of p-type material may be used if desired, but is not required.Substrate 16 may be formed of, for example, Si, SiGe, Ge, or GaAs.Typically the entire substrate 16 is p-type doped silicon substrate andmay contain a surface p-well 20 (with layer 18 omitted), but many otheroptions are possible, such as, for example p on p− substrates, p on p+substrates, p-wells in n-type substrates or the like. The terms wafer orsubstrate used in the description includes any semiconductor-basedstructure having an exposed surface in which to form the circuitstructure used in the invention. Wafer and substrate are to beunderstood as including silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a wafer or substrate in the following description,previous process steps may have been utilized to form regions/junctionsin the base semiconductor structure or foundation.

[0012] An insulating layer 22 such as, for example, silicon dioxide isformed on the upper surface of p-well 20. The p-type layer may be ap-well formed in substrate 16. A photogate 24 thin enough to passradiant energy or of a material which passes radiant energy is formed onthe insulating layer 22. The photogate 24 receives an applied controlsignal PG which causes the initial accumulation of pixel charges in n+region 26. The n+ type region 26, adjacent one side of photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below.

[0013] A reset gate 32 is also formed on insulating layer 22 adjacentand between n+ type region 30 and another n+ region 34 which is alsoformed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form areset transistor 31 which is controlled by a reset signal RST. The n+type region 34 is coupled to voltage source V_(DD), e.g., 5 volts. Thetransfer and reset transistors 29, 31 are n-channel transistors asdescribed in this implementation of a CMOS imager circuit in a p-well.It should be understood that it is possible to implement a CMOS imagerin an n-well in which case each of the transistors would be p-channeltransistors. It should also be noted that while FIG. 1 shows the use ofa transfer gate 28 and associated transistor 29, this structure providesadvantages, but is not required.

[0014] Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage sourceV_(DD) and the drain of transistor 38 coupled to a lead 42. The drain ofrow select transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source V_(SS), e.g. 0 volts. Transistor 39 is kept on by asignal V_(LN) applied to its gate.

[0015] The imager includes a readout circuit 60 which includes a signalsample and hold (S/H) circuit including a S/H n-channel field effecttransistor 62 and a signal storage capacitor 64 connected to the sourcefollower transistor 36 through row transistor 38. The other side of thecapacitor 64 is connected to a source voltage V_(SS). The upper side ofthe capacitor 64 is also connected to the gate of a p-channel outputtransistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeV_(OUTS) and through a load transistor 70 to the voltage supply V_(DD).A signal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0016] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageV_(SS). The upper side of the capacitor 74 is also connected to the gateof a p-channel output transistor 76. The drain of the output transistor76 is connected through a p-channel column select transistor 78 to areset sample output node V_(OUTR) and through a load transistor 80 tothe supply voltage V_(DD). A signal called “reset sample and hold” (SHR)briefly turns on the S/H transistor 72 immediately after the resetsignal RST has caused reset transistor 31 to turn on and reset thepotential of the floating diffusion node 30, so that the capacitor 74stores the voltage to which the floating diffusion node 30 has beenreset.

[0017] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by reset transistor 31 and then of the stored chargefrom the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages V_(OUTR) and V_(OUTS) of thereadout circuit 60. These voltages are then subtracted(V_(OUTS)−V_(OUTR)) by subtractor 82 to provide an output signalterminal 81 which is an image signal independent of pixel to pixelvariations caused by fabrication variations in the reset voltagetransistor 31 which might cause pixel to pixel variations in the outputsignal.

[0018]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in the mannershown by element 14 of FIG. 1. FIG. 4 shows a 2×2 portion of pixel array200. Pixel array 200 comprises a plurality of pixels arranged in apredetermined number of columns and rows. The pixels of each row inarray 200 are all turned on at the same time by a row select line, e.g.,line 86, and the pixels of each column are selectively output by acolumn select line, e.g., line 42. A plurality of rows and column linesare provided for the entire array 200. The row lines are selectivelyactivated by the row driver 210 in response to row address decoder 220and the column select lines are selectively activated by the columndriver 260 in response to column address decoder 270. Thus, a row andcolumn address is provided for each pixel. The CMOS imager is operatedby the control circuit 250 which controls address decoders 220, 270 forselecting the appropriate row and column lines for pixel readout, androw and column driver circuitry 210, 260 which apply driving voltage tothe drive transistors of the selected row and column lines.

[0019]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and pulsed from5V to 0V during integration. The reset signal RST is nominally set at2.5V. As can be seen from the figure, the process is begun at time to bybriefly pulsing reset voltage RST to 5V. The RST voltage, which isapplied to the gate 32 of reset transistor 31, causes transistor 31 toturn on and the floating diffusion node 30 to charge to the V_(DD)voltage present at n+ region 34 (less the voltage drop V_(TH) oftransistor 31). This resets the floating diffusion node 30 to apredetermined voltage (V_(DD)-V_(TH)). The charge on floating diffusionnode 30 is applied to the gate of the source follower transistor 36 tocontrol the current passing through transistor 38, which has been turnedon by a row select (ROW) signal, and load transistor 39. This current istranslated into a voltage on line 42 which is next sampled by providinga SHR signal to the S/H transistor 72 which charges capacitor 74 withthe source follower transistor output voltage on line 42 representingthe reset charge present at floating diffusion node 30. The PG signal isnext pulsed to 0 volts, causing charge to be collected in n+ region 26.

[0020] A transfer gate voltage TX, similar to the reset pulse RST, isthen applied to transfer gate 28 of transistor 29 to cause the charge inn+ region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also be notedthat CMOS imagers may dispense with the transfer gate 28 and associatedtransistor 29, or retain these structures while biasing the transfertransistor 29 to an always “on” state.

[0021] The operation of the charge collection of the CMOS imager isknown in the art and is described in several publications such as Mendiset al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172,pp. 19-29 (1994); Mendis et al., “CMOS Active Pixel Image Sensors forHighly Integrated Imaging Systems,” IEEE Journal of Solid StateCircuits, Vol. 32(2) (1997); and Eric R Fossum, “CMOS Image Sensors:Electronic Camera on a Chip,” IEDM Vol. 95, pp. 17-25 (1995) as well asother publications. These references are incorporated herein byreference.

[0022] Quantum efficiency is a problem in some imager applications dueto the diffusion of signal carriers out of the photosite and into thesubstrate, where they become effectively lost. The loss of signalcarriers results in decreased signal strength, increased cross talk, andthe reading of an improper value for the adjacent pixels.

[0023] There is needed, therefore, an improved pixel sensor cell for usein an imager that exhibits improved quantum efficiency, a bettersignal-to-noise ratio, and reduced cross talk. A method of fabricating apixel sensor cell exhibiting these improvements is also needed.

SUMMARY OF THE INVENTION

[0024] The present invention provides a pixel sensor cell formed in aretrograde well in a semiconductor substrate having improved quantumefficiency, an improved signal-to-noise ratio, and reduced cross talk.The retrograde well comprises a doped region with a vertically gradeddopant concentration that is lowest at the substrate surface, andhighest at the bottom of the well. The retrograde well would have anentire array of pixels formed therein, and may also have peripheralcircuitry formed therein. If the peripheral circuitry is formed in theretrograde well, the well may have a different dopant profile in theperipheral region than in the array region. The highly concentratedregion at the bottom of the retrograde well reflects signal carriersback to the photosensor so that they are not lost to the substrate. Alsoprovided are methods for forming a pixel sensor cell in the retrogradewell of the present invention.

[0025] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a representative circuit of a CMOS imager.

[0027]FIG. 2 is a block diagram of a CMOS pixel sensor chip.

[0028]FIG. 3 is a representative timing diagram for the CMOS imager.

[0029]FIG. 4 is a representative pixel layout showing a 2×2 pixellayout.

[0030]FIG. 5 is a cross-sectional view of two pixel sensor cellsaccording to an embodiment of the present invention.

[0031]FIG. 6 is a graph depicting the dopant concentration as a functionof the depth of the retrograde well.

[0032]FIG. 7 is a cross-sectional view of a semiconductor waferundergoing the process of a preferred embodiment of the invention.

[0033]FIG. 8 shows the wafer of FIG. 7 at a processing step subsequentto that shown in FIG. 7.

[0034]FIG. 9 is a cross-sectional view of a semiconductor waferundergoing the process of a second embodiment of the invention.

[0035]FIG. 10 shows the wafer of FIG. 9 at a processing step subsequentto that shown in FIG. 9.

[0036]FIG. 11 is an illustration of a computer system having a CMOSimager according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0037] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0038] The terms “wafer” and “substrate” are to be understood asincluding silicon-on-insulator (SOI) or silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processsteps may have been utilized to form regions or junctions in the basesemiconductor structure or foundation. In addition, the semiconductorneed not be silicon-based, but could be based on silicon-germanium,germanium, or gallium arsenide. For exemplary purposes an imager formedof n-channel devices in a retrograde p-well is illustrated anddescribed, but it should be understood that the invention is not limitedthereto, and may include other combinations such as an imager formed ofp-channel devices in a retrograde n-well.

[0039] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

[0040] The structure of pixel cells 14 formed in retrograde wells 20 ofthe first embodiment are shown in more detail in FIG. 5. A pixel cell 14may be formed in a substrate 16 having a retrograde layer or well 20 ofa first conductivity type, which for exemplary purposes is treated asp-type. The retrograde well 20 has a vertically graded dopantconcentration that is lowest at the substrate surface, and highest atthe bottom of the well, as is shown in FIG. 6. The dopant concentrationat the top of the retrograde well 20 is within the range of about 5×10¹⁴to about 1×10¹⁷ atoms per cm³, and is preferably within the range ofabout 1×10¹⁵ to about 5×10¹⁶ atoms per cm³, and most preferably is about5×10¹⁵ atoms per cm³. At the bottom of the retrograde well 20, thedopant concentration is within the range of about 1×10¹⁶ to about 2×10¹⁸atoms per cm³, and is preferably within the range of about 5×10¹⁶ toabout 1×10¹⁸ atoms per cm³, and most preferably is about 3×10¹⁷ atomsper cm³. A single retrograde well 20 as depicted in FIG. 5, spans allpixels in the array of pixels.

[0041] A second retrograde well (not shown) may be formed in thesubstrate 16, and may have peripheral circuitry, such as, e.g., logiccircuitry, formed therein. This second well may be doped similarly ordifferently from the first retrograde well 20, for example, the firstretrograde well 20 may be doped to a first dopant level such as about3×10¹⁷ atoms per cm³ at the bottom of the well and the second well maybe doped to a second dopant level such as 5×10¹⁶ at the bottom of thewell.

[0042] The transistor gates form the pixel cell 14 as shown: a photogate24, a transfer gate 28 for transfer transistor 29, and a resettransistor gate 32 for the reset transistor 31. In addition, thephotosensitive element in the pixel cell 14 is shown to be a photogate24, but other photosensitive elements such as a photodiode or aphotoconductor could be used. The source follower transistor and the rowselect transistor are not shown. The transfer gate 28 and the reset gate32 include a gate oxide layer 106 on the retrograde well 20, and aconductive layer 108 of doped polysilicon, tungsten, or other suitablematerial over the gate oxide layer 106. An insulating cap layer 110 of,for example, silicon dioxide, silicon nitride, or ONO(oxide-nitride-oxide), may be formed if desired; also a more conductivelayer such as a silicide layer (not shown) may be used between theconductive layer 108 and the cap 110 of the transfer gate stack 28,source follower gate, row select gate, and reset gate stack 32, ifdesired. Insulating sidewalls 112 are also formed on the sides of thegate stacks 28, 32. These sidewalls may be formed of, for example,silicon dioxide or silicon nitride or ONO. The transfer gate is notrequired but may advantageously be included. The photogate 24 is asemitransparent conductor and is shown as an overlapping gate. In thiscase there is a second gate oxide 105 over the retrograde well and underthe photogate.

[0043] Underlying the photogate 24 is a doped region 26 called thephotosite, where photogenerated charges are stored. In between the resettransistor gate 32 and the transfer gate 28 is a doped region 30 that isthe source for the reset transistor 31, and on the other side of thereset transistor gate 32 is a doped region 34 that acts as a drain forthe reset transistor 31. The doped regions 26, 30, 34 are doped to asecond conductivity type, which for exemplary purposes is treated asn-type. The second doped region 30 is the floating diffusion region,sometimes also referred to as a floating diffusion node, and it servesas the source for the reset transistor 31. The third doped region 34 isthe drain of the reset transistor 31, and is also connected to voltagesource Vdd.

[0044] As shown in FIG. 5, as light radiation 12 in the form of photonsstrikes the photosite 26, photo-energy is converted to electricalsignals, i.e., carriers 120, which are stored in the photosite 26. Theabsorption of light creates electron-hole pairs. For the case of ann-doped photosite in a p-well, it is the electrons that are stored. Forthe case of a p-doped photosite in an n-well, it is the holes that arestored. In the exemplary pixel cell 14 having n-channel devices formedin a p-type retrograde well 20, the carriers 120 stored in the photosite26 are electrons. The retrograde well 20 acts to reduce carrier loss tothe substrate 16 by forming a concentration gradient that modifies theband diagram and serves to reflect electrons back towards the photosite26, thereby increasing quantum efficiency of the pixel 14.

[0045] The retrograde well 20 is manufactured through a processdescribed as follows, and illustrated by FIGS. 7 and 8. Referring now toFIG. 7, a substrate 16, which may be any of the types of substratesdescribed above, is provided. Retrograde well 20 is then formed bysuitable means such as blanket ion implantation of the entire wafer. Theretrograde well 20 may be implanted at a later stage of the process suchas after field oxide formation. The implant may be patterned so that thearray well and the periphery logic well could have different dopingprofiles.

[0046] Ion implantation is performed by placing the substrate 16 in anion implanter, and implanting appropriate dopant ions into the substrate16 at an energy of 100 keV to 5 MeV to form retrograde wells 20 having adopant concentration that is lowest at the surface, and highest at thebottom of the well. The dopant concentration at the top of theretrograde well 20 is within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³, and is preferably within the range of about 1×10¹⁵ toabout 5×10¹⁶ atoms per cm³, and most preferably is about 5×10¹⁵ atomsper cm³. At the bottom of the retrograde well 20, the dopantconcentration is within the range of about 1×10¹⁶ to about 2×10¹⁸ atomsper cm³, and is preferably within the range of about 5×10¹⁶ to about1×10¹⁸ atoms per cm³, and most preferably is about 3×10¹⁷ atoms per cm³.If the retrograde well is to be a p-type well, a p-type dopant, such asboron, is implanted, and if the well 20 is to be an n-type well, ann-type dopant, such as arsenic, antimony, or phosphorous is implanted.The resultant structure is shown in FIG. 8. Multiple high energyimplants may be used to tailor the profile of the retrograde well 20.

[0047] Referring now to FIGS. 9 and 10, field oxide regions 114 may beformed around the pixel cell 14 prior to the formation of the retrogradewell 20. The field oxide regions are formed by any known technique suchas thermal oxidation of the underlying silicon in a LOCOS process or byetching trenches and filling them with oxide in an STI process.Following field oxide 114 formation, the retrograde wells 20 may then beformed by blanket implantation as shown in FIG. 10 or by maskedimplantation (not shown).

[0048] Subsequent to formation of the retrograde well 20, the devices ofthe pixel sensor cell 14, including the photogate 24, the transfer gate28, reset transistor 31, the source follower 36 and the row selecttransistor 38 are formed by well-known methods. Doped regions 26, 30,and 34 are formed in the retrograde well 20, and are doped to a secondconductivity type, which for exemplary purposes will be considered to ben-type. The doping level of the doped regions 26, 30, 34 may vary butshould be higher than the doping level at the top of the retrograde well20, and greater than 5×10¹⁶ atoms per cm³. If desired, multiple masksand resists may be used to dope these regions to different levels. Dopedregion 26 may be variably doped, such as either n+ or n− for ann-channel device. Doped region 34 should be strongly doped, i.e., for ann-channel device, the doped region 34 will be doped as n+. Doped region30 is typically strongly doped (n+), and would not be lightly doped (n−)unless a buried contact is also used.

[0049] The pixel sensor cell 14 is essentially complete at this stage,and conventional processing methods may be used to form contacts andwiring to connect gate lines and other connections in the pixel cell 14.For example, the entire surface may then be covered with a passivationlayer of, e.g., silicon dioxide, BSG, PSG, or BPSG, which is CMPplanarized and etched to provide contact holes, which are thenmetallized to provide contacts to the photogate, reset gate, andtransfer gate. Conventional multiple layers of conductors and insulatorsmay also be used to interconnect the structures in the manner shown inFIG. 1.

[0050] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at400 in FIG. 11. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision system, vehicle navigation system, videotelephone, surveillance system, auto focus system, star tracker system,motion detection system, image stabilization system and data compressionsystem for high-definition television, all of which can utilize thepresent invention.

[0051] A processor system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 444, e.g., amicroprocessor, that communicates with an input/output (I/O) device 446over a bus 452. The CMOS imager 442 also communicates with the systemover bus 452. The computer system 400 also includes random access memory(RAM) 448, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 454 and a compact disk (CD) ROMdrive 456 which also communicate with CPU 444 over the bus 452. CMOSimager 442 is preferably constructed as an integrated circuit whichincludes pixels containing a photosensor such as a photogate orphotodiode formed in a retrograde well, as previously described withrespect to FIGS. 5 through 10. The CMOS imager 442 may be combined witha processor, such as a CPU, digital signal processor or microprocessor,with or without memory storage in a single integrated circuit, or may beon a different chip than the processor.

[0052] As can be seen by the embodiments described herein, the presentinvention encompasses a pixel sensor cell formed in a retrograde well.The pixel sensor cell has improved quantum efficiency and an improvedsignal-to-noise ratio due to the presence of a doping gradient inducedelectric field created in the bottom of the retrograde well whichreflects signal carriers back to the photosensitive node. By reflectingphotogenerated carriers back to the storage node the retrograde p-wellalso reduces the number of carriers diffusing to adjacent pixels and soalso reduces cross talk.

[0053] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion region, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Similarly,the process described above is but one method of many that could beused. The above description and drawings illustrate preferredembodiments which achieve the objects, features and advantages of thepresent invention. It is not intended that the present invention belimited to the illustrated embodiments. Any modification of the presentinvention which comes within the spirit and scope of the followingclaims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A pixel sensor cell for an imaging device, saidpixel sensor cell comprising: a retrograde well of a first conductivitytype formed in a substrate; a photosensitive region formed in saidretrograde well; and a floating diffusion region of a secondconductivity type formed in said retrograde well for receiving chargestransferred from said photosensitive region.
 2. The pixel sensor cell ofclaim 1, wherein the first conductivity type is p-type, and the secondconductivity type is n-type.
 3. The pixel sensor cell of claim 2,wherein said retrograde well is doped with boron.
 4. The pixel sensorcell of claim 1, wherein the first conductivity type is n-type, and thesecond conductivity type is p-type.
 5. The pixel sensor cell of claim 4,wherein said retrograde well is doped with a dopant selected from thegroup consisting of arsenic, antimony, and phosphorous.
 6. The pixelsensor cell of claim 1, wherein said retrograde well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 7. The pixel sensor cell ofclaim 6, wherein said retrograde well has a dopant concentration withinthe range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at the top ofsaid retrograde well.
 8. The pixel sensor cell of claim 1, wherein saidretrograde well has a dopant concentration within the range of about5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of said retrogradewell.
 9. The pixel sensor cell of claim 8, wherein said retrograde wellhas a dopant concentration within the range of about 1×10¹⁵ to about5×10¹⁶ atoms per cm³ at the top of said retrograde well.
 10. The pixelsensor cell of claim 1, wherein said retrograde well has a dopantconcentration of about 3×10¹⁷ atoms per cm³ at the bottom of saidretrograde well.
 11. The pixel sensor cell of claim 10, wherein saidretrograde well has a dopant concentration of about 5×10¹⁵ atoms per cm³at the top of said retrograde well.
 12. The pixel sensor cell of claim1, further comprising a photosensor formed on said photosensitive regionfor controlling the collection of charges in said photosensitive region.13. The pixel sensor cell of claim 12, wherein said photosensor is aphotodiode sensor.
 14. The pixel sensor cell of claim 12, wherein saidphotosensor is a photogate sensor.
 15. The pixel sensor cell of clam 12,wherein said photosensor is a photoconductor sensor.
 16. The pixelsensor cell of claim 1, further comprising a transfer gate formed onsaid retrograde well between said photosensor and said floatingdiffusion region.
 17. The pixel sensor cell of claim 1, furthercomprising a reset transistor formed in said retrograde well forperiodically resetting a charge level of said floating diffusion region,said floating diffusion region being the source of said resettransistor.
 18. The pixel sensor cell of claim 1, wherein saidphotosensitive region comprises a doped region of a second conductivitytype.
 19. A pixel sensor cell for an imaging device, said pixel sensorcell comprising: a retrograde well of a first conductivity type formedin a substrate; a photosensor formed in said retrograde well; a resettransistor having a gate stack formed in said retrograde well; afloating diffusion region of a second conductivity type formed in saidretrograde well between said photosensor and reset transistor forreceiving charges from said photosensor, said reset transistor operatingto periodically reset a charge level of said floating diffusion region;and an output transistor having a gate electrically connected to saidfloating diffusion region.
 20. The pixel sensor cell of claim 19,wherein said photosensor further comprises a doped region of a secondconductivity type located in said retrograde well.
 21. The pixel sensorcell of claim 19, wherein said photosensor is a photodiode sensor. 22.The pixel sensor cell of claim 19, wherein said photosensor is aphotoconductor sensor.
 23. The pixel sensor cell of claim 19, furthercomprising a transfer gate located between said photosensor and saidfloating diffusion region.
 24. The pixel sensor cell of claim 23,wherein said photosensor is a photogate sensor.
 25. The pixel sensorcell of claim 19, wherein the first conductivity type is p-type, and thesecond conductivity type is n-type.
 26. The pixel sensor cell of claim25, wherein said retrograde well is doped with boron.
 27. The pixelsensor cell of claim 19, wherein the first conductivity type is n-type,and the second conductivity type is p-type.
 28. The pixel sensor cell ofclaim 27, wherein said retrograde well is doped with a dopant selectedfrom the group consisting of arsenic, antimony, and phosphorous.
 29. Thepixel sensor cell of claim 19, wherein said retrograde well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the bottom of said retrograde well.
 30. The pixel sensor cell ofclaim 29, wherein said retrograde well has a dopant concentration withinthe range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at the top ofsaid retrograde well.
 31. The pixel sensor cell of claim 19, whereinsaid retrograde well has a dopant concentration within the range ofabout 5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of saidretrograde well.
 32. The pixel sensor cell of claim 31, wherein saidretrograde well has a dopant concentration within the range of about1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at the top of said retrograde well.33. The pixel sensor cell of claim 19, wherein said retrograde well hasa dopant concentration of about 3×10¹⁷ atoms per cm³ at the bottom ofsaid retrograde well.
 34. The pixel sensor cell of claim 31, whereinsaid retrograde well has a dopant concentration of about 5×10¹⁵ atomsper cm³ at the top of said retrograde well.
 35. A CMOS imagercomprising: a substrate having at least one retrograde well of a firstconductivity type; an array of pixel sensor cells formed in said atleast one retrograde well, wherein each pixel sensor cell has aphotosensor; and a circuit electrically connected to receive and processoutput signals from said array.
 36. The CMOS imager of claim 35, whereinsaid at least one retrograde well comprises one retrograde well.
 37. TheCMOS imager of claim 35, wherein said at least one retrograde wellcomprises a plurality of retrograde wells, wherein said array is formedin a first retrograde well of said plurality and said circuit is formedin a second retrograde well of said plurality.
 38. The CMOS imager ofclaim 37, wherein said first retrograde well is doped to a first dopantlevel, and said second retrograde well is doped to a second dopantlevel.
 39. The CMOS imager of claim 35, wherein each pixel sensorfurther comprises a floating diffusion region of a second conductivitytype located in said at least one retrograde well.
 40. The CMOS imagerof claim 39, wherein the first conductivity type is p-type, and thesecond conductivity type is n-type.
 41. The CMOS imager of claim 40,wherein said at least one retrograde well is doped with boron.
 42. TheCMOS imager of claim 39, wherein the first conductivity type is n-type,and the second conductivity type is p-type.
 43. The CMOS imager of claim42, wherein said at least one retrograde well is doped with a dopantselected from the group consisting of arsenic, antimony, andphosphorous.
 44. The CMOS imager of claim 35, wherein each pixel sensorcell further comprises a transfer gate located between said photosensorand said floating diffusion region.
 45. The CMOS imager of claim 44,wherein the photosensors are photogate sensors.
 46. The CMOS imager ofclaim 35, wherein said at least one retrograde well has a dopantconcentration within the range of about 1×10¹⁶ to about 2×10¹⁸ atoms percm³ at the bottom of said at least one retrograde well.
 47. The CMOSimager of claim 46, wherein said at least one retrograde well has adopant concentration within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³ at the top of said at least one retrograde well.
 48. TheCMOS imager of claim 35, wherein said at least one retrograde well has adopant concentration within the range of about 5×10¹⁶ to about 1×10¹⁸atoms per cm³ at the bottom of said at least one retrograde well. 49.The CMOS imager of claim 48, wherein said at least one retrograde wellhas a dopant concentration within the range of about 1×10¹⁵ to about5×10¹⁶ atoms per cm³ at the top of said at least one retrograde well.50. The CMOS imager of claim 35, wherein said at least one retrogradewell has a dopant concentration of about 3×10¹⁷ atoms per cm³ at thebottom of said at least one retrograde well.
 51. The CMOS imager ofclaim 50, wherein said at least one retrograde well has a dopantconcentration of about 5×10¹⁵ atoms per cm³ at the top of said at leastone retrograde well.
 52. The CMOS imager of claim 35, wherein thephotosensors are photodiode sensors.
 53. The CMOS imager of claim 35,wherein the photosensors are photoconductor sensors.
 54. An imagercomprising: an array of pixel sensor cells formed in a substrate havingat least one retrograde well of a first conductivity type, wherein eachpixel sensor cell has a photosensor; a circuit formed in the substrateand electrically connected to the array for receiving and processingsignals representing an image output by the array and for providingoutput data representing the image; and a processor for receiving andprocessing data representing the image.
 55. The imager of claim 54,wherein said array, said circuit, and said processor are formed on asingle substrate.
 56. The imager of claim 54, wherein said array andsaid circuit are formed on a first substrate, and said processor isformed on a second substrate.
 57. The imager of claim 54, wherein saidat least one retrograde well comprises one retrograde well.
 58. Theimager of claim 54, wherein said at least one retrograde well comprisesa plurality of retrograde wells, wherein said array is formed in a firstretrograde well of said plurality and said circuit is formed in a secondretrograde well of said plurality.
 59. The imager of claim 57, whereinsaid first retrograde well is doped to a first dopant level, and saidsecond retrograde well is doped to a second dopant level.
 60. The imagerof claim 54, wherein each pixel sensor cell further comprises a floatingdiffusion region of a second conductivity type located in said at leastone retrograde well.
 61. The imager of claim 60, wherein the firstconductivity type is p-type, and the second conductivity type is n-type.62. The imager of claim 60, wherein the first conductivity type isn-type, and the second conductivity type is p-type.
 63. The imager ofclaim 54, wherein each pixel sensor cell further comprises a transfergate located between said photosensor and said floating diffusionregion.
 64. The imager of claim 63, wherein the photosensors arephotogate sensors.
 65. The imager of claim 54, wherein said at least oneretrograde well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the bottom of said at least oneretrograde well, and within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³ at the top of said at least one retrograde well.
 66. Theimager of claim 54, wherein said at least one retrograde well has adopant concentration within the range of about 5×10¹⁶ to about 1×10¹⁸atoms per cm³ at the bottom of said at least one retrograde well, andwithin the range of about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³ at thetop of said at least one retrograde well.
 67. The imager of claim 54,wherein said at least one retrograde well has a dopant concentration ofabout 3×10¹⁷ atoms per cm³ at the bottom of said at least one retrogradewell, and about 5×10¹⁵ atoms per cm³ at the top of said at least oneretrograde well.
 68. The imager of claim 54, wherein the photosensorsare photodiode sensors.
 69. The imager of claim 54, wherein thephotosensors are photoconductor sensors.
 70. An imager comprising: aCMOS imager comprising an array of pixel sensor cells formed in aretrograde well on a substrate, wherein each pixel sensor cell has aphotosensitive region, a photosensor formed on the photosensitiveregion, and a floating diffusion region for receiving and outputtingimage charge received from the photosensitive region, and a circuitformed in the substrate and electrically connected to the array forreceiving and processing signals representing an image output by thearray and for providing output data representing the image; and aprocessor for receiving and processing data representing the image. 71.The imager of claim 70, wherein said CMOS imager and said processor areformed on a single substrate.
 72. The imager of claim 70, wherein saidCMOS imager is formed on a first substrate, and said processor is formedon a second substrate.
 73. The imager of claim 70, wherein theretrograde well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the bottom of the retrogradewell.
 74. The imager of claim 73, wherein the retrograde well has adopant concentration within the range of about 5×10¹⁴ to about 1×10¹⁷atoms per cm³ at the top of the retrograde well.
 75. The imager of claim70, wherein the retrograde well has a dopant concentration within therange of about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of theretrograde well.
 76. The imager of claim 75, wherein the retrograde wellhas a dopant concentration within the range of about 1×10¹⁵ to 5×10¹⁶atoms per cm³ at the top of the retrograde well.
 77. The imager of claim70, wherein the retrograde well has a dopant concentration of about3×10¹⁷ atoms per cm³ at the bottom of the retrograde well.
 78. Theimager of claim 77, wherein the retrograde well has a dopantconcentration of about 5×10¹⁵ atoms per cm³ at the top of the retrogradewell.
 79. The imager of claim 70, wherein the retrograde well is a firstretrograde well, and said circuit is formed in a second retrograde well.80. A method of forming a photosensor for an imaging device, said methodcomprising the steps of: forming a retrograde well of a firstconductivity type in a substrate; and forming a photosensor at an uppersurface of the retrograde well.
 81. The method of claim 80, wherein saidstep of forming a retrograde well is an ion implantation step.
 82. Themethod of claim 80, wherein the first conductivity type is p-type. 83.The method of claim 82, wherein the retrograde well is doped with boron.84. The method of claim 76, wherein the first conductivity type isn-type.
 85. The method of claim 84, wherein the retrograde well is dopedwith a dopant selected from the group consisting of arsenic, antimony,and phosphorous.
 86. The method of claim 80, wherein the retrograde wellhas a dopant concentration within the range of about 1×10¹⁶ to about2×10¹⁸ atoms per cm³ at the bottom of the retrograde well, and withinthe range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³ at the top ofthe retrograde well.
 87. The method of claim 80, wherein the retrogradewell has a dopant concentration within the range of about 5×10¹⁶ to abut1×10¹⁸ atoms per cm³ at the bottom of the retrograde well, and withinthe range of about 1×10¹⁵ to 5×10¹⁶ atoms per cm³ at the top of theretrograde well.
 88. The method of claim 80, wherein the retrograde wellhas a dopant concentration of about 3×10¹⁷ atoms per cm³ at the bottomof the retrograde well, and about 5×10¹⁵ is atoms per cm³ at the top ofthe retrograde well.
 89. The method of claim 80, wherein the photosensorforming step is a photodiode sensor forming step.
 90. The method ofclaim 80, wherein the photosensor forming step is a photoconductorforming step.
 91. The method of claim 80, wherein the photosensorfurther comprises a transfer gate.
 92. The method of claim 86, whereinthe photosensor forming step is a photogate sensor forming step.
 93. Amethod of forming a pixel sensor cell for an imaging device, said methodcomprising the steps of: forming a retrograde well of a firstconductivity type in a substrate; forming a photosensitive region in theretrograde well; forming a photosensor on an upper surface of thephotosensitive region for controlling the collection of charge therein;and forming a floating diffusion region of a second conductivity type inthe retrograde well for receiving charges transferred from saidphotosensitive region.
 94. The method of claim 93, wherein said step offorming a retrograde well is an ion implantation step.
 95. The method ofclaim 93, wherein the first conductivity type is p-type, and the secondconductivity type is n-type.
 96. The method of claim 95, wherein theretrograde well is doped with boron.
 97. The method of claim 93, whereinthe first conductivity type is n-type, and the second conductivity typeis p-type.
 98. The method of claim 97, wherein the retrograde well isdoped with a dopant selected from the group consisting of arsenic,antimony, and phosphorous.
 99. The method of claim 93, wherein theretrograde well has a dopant concentration within the range of about1×10¹⁶ to about 2×10¹¹ atoms per cm³ at the bottom of the retrogradewell, and within the range of about 5×10¹⁴ to about 1×10¹⁷ atoms per cm³at the top of the retrograde well.
 100. The method of claim 93, whereinthe retrograde well has a dopant concentration within the range of about5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of the retrogradewell, and within the range of about 1×10¹⁵ to about 5×10¹⁶ atoms per cm³at the top of the retrograde well.
 101. The method of claim 93, whereinthe retrograde well has a dopant concentration of about 3×10¹⁷ atoms percm³ at the bottom of the retrograde well, and about 5×10¹⁵ atoms per cm³at the top of the retrograde well.
 102. The method of claim 93, whereinthe photosensor is a photodiode sensor.
 103. The method of claim 93,wherein the photosensor is a photoconductor sensor.
 104. The method ofclaim 93, further comprising a step of forming a transfer gate on theretrograde well between the photosensor and the floating diffusionregion.
 105. The method of claim 104, wherein the photosensor is aphotogate sensor.
 106. The method of claim 93, further comprising a stepof forming a reset transistor in the retrograde well for periodicallyresetting a charge level of the floating diffusion region, said floatingdiffusion region being the source of the reset transistor.
 107. Themethod of claim 93, wherein the photosensitive region comprises a dopedregion of a second conductivity type.
 108. A method of forming a pixelarray for an imaging device, said method comprising the steps of:forming a retrograde well of a first conductivity type in a substrate;and forming a plurality of pixel sensor cells in the retrograde well,wherein each pixel sensor cell has a photosensitive region, aphotosensor formed on the photosensitive region, and a floatingdiffusion region of a second conductivity type.
 109. The method of claim108, wherein said step of forming a retrograde well is an ionimplantation step.
 110. The method of claim 108, wherein the firstconductivity type is p-type, and the second conductivity type is n-type.111. The method of claim 108, wherein the first conductivity type isn-type, and the second conductivity type is p-type.
 112. The method ofclaim 108, wherein the retrograde well has a dopant concentration withinthe range of about 1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the bottom ofthe retrograde well, and within the range of about 5×10¹⁴ to about1×10¹⁷ atoms per cm³ at the top of the retrograde well.
 113. The methodof claim 108, wherein the retrograde well has a dopant concentrationwithin the range of about 5×10¹⁶ to about 1×10¹⁸ atoms per cm³ at thebottom of the retrograde well, and within the range of about 1×10¹⁵ toabout 5×10¹⁶ atoms per cm³ at the top of the retrograde well.
 114. Themethod of claim 108, wherein the retrograde well has a dopantconcentration of about 3×10¹⁷ atoms per cm³ at the bottom of theretrograde well, and about 5×10¹⁵ atoms per cm³ at the top of theretrograde well.
 115. The method of claim 108, wherein thephotosensitive region comprises a doped region of a second conductivitytype.
 116. The method of claim 108, wherein the photosensor of eachpixel sensor cell is a photodiode sensor.
 117. The method of claim 108,wherein the photosensor of each pixel sensor cell is a photoconductorsensor.
 118. The method of claim 108, further comprising a step offorming a transfer gate for each pixel sensor cell on the retrogradewell between the photosensor and the floating diffusion region.
 119. Themethod of claim 118, wherein the photosensor of each pixel sensor cellis a photogate sensor.